1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention relates to an electrostatic discharge protection device and a method of fabricating the same.
2. Description of the Related Art
An integrated circuit (IC) including a MOS field effect transistor (MOSFET) may be easily damaged by an electrostatic discharge (ESD). An ESD may be delivered to an IC from an input/output (I/O) pin, a power pin, or a pad of another IC, and may attack a junction of a transistor, a dielectric and a unit device.
Various structures of an ESD protection circuit have been developed to protect devices from an ESD. An important role of an ESD protection circuit is to guide the ESD current from an easily attackable circuit to a low-impedance path.
Such an ESD protection circuit may be connected between an I/O and power pins and an internal circuit in parallel, and functions to guide the ESD current to an external region by providing a current path at a low power during an ESD. A representative discharge protection circuit may be categorized into a silicon controlled rectifier (SCR) and an npn bipolar transistor. An SCR instantly discharges an ESD current to a node Vss using a parasitic npnp diode. An npn bipolar transistor discharges an ESD current to a node Vss by an operation of a parasitic npn bipolar transistor of a MOS transistor based on a snap-back phenomenon. Such an ESD protection circuit may use a gate grounded NMOS transistor (ggNMOS) for a structure of the npn bipolar transistor.
FIG. 1 is a circuit diagram of a conventional ESD protection circuit using a ggNMOS transistor. FIG. 2 is a graph illustrating a voltage-current (V-I) characteristic of the ggNMOS transistor of FIG. 1 when an electrostatic current is discharged.
Referring to FIG. 1, an ESD protection circuit 5 is connected in parallel between a pad 1 and an internal circuit 3. A drain of the ggNMOS transistor is electrically connected to a pad 1. A gate, a source and a channel of the transistor are connected to a ground node Vss.
Referring to FIG. 2, when a voltage higher than a trigger voltage Vt is applied to the ggNMOS transistor by an ESD, a break down of the drain junction in the ggNMOS transistor causes a portion of charges to flow in a substrate. The charges make the parasitic npn transistor turned-on to discharge a large amount of ESD current through a low-impedance path to the Vss node instantly. Therefore, the internal circuit 3 is protected from damage.
Three issues may degrade the robustness of an ESD protection device. These issues are an increase of a surface current density during an ESD, a hot-carrier issue and Joule heating. In an effort to solve this problem, a silicide blocking layer may be formed between the gate and the source/drain contact of the ggNMOS. However, such a structure requires that the silicide be separated at an area where the source/drain contact is connected to a gate. Further, such a structure has a disadvantage of increasing an area of the ESD circuit.
FIG. 3 illustrates another conventional semiconductor device for an ESD protection device having an n+ drain surrounded by an n-diffusion layer without increasing a layout area.
Referring to FIG. 3, the ESD protection device is formed at a p-well 12 of a substrate 10 and includes NMOS transistors T1 and T2 connected in series sharing an n+ drain 20. Each NMOS transistor T1 and T2 includes a gate electrode 14. Sources 16 of each of the NMOS transistors T1 and T2 and a p+ guard ring 18 are connected to a node Vss. The n+ drain 20 is electrically connected to a pad 24. The device includes an n-diffusion layer 22 surrounding the n+ drain 20 to overcome an increase of surface current density and a hot carrier issue. The n− diffusion layer 22 includes a space under the n+ drain 20.
The space under the n+ drain 20 has a relatively low breakdown voltage. Therefore, the substrate current is generated through the space when an ESD voltage is applied to the n+ drain 20 and discharged through parasitic npn bipolar transistors Q1 and Q2 in the NMOS transistor to the node Vss. This structure may improve ESD robustness because a current path is separated from a substrate surface and a transistor channel that are relatively weak. However, such a structure is formed through a complicated process because it requires an additional layer for forming the n-diffusion layer 22 having the space under the n+ drain 20.